The present invention relates to semiconductor fabrication and in particular to fabrication of an interconnect with dielectric barrier.
Electrically conductive lines for, for example, signal transferring are essential in electrical devices as well as in semiconductor integrated circuit (IC) devices. The electrically conductive lines on different levels are connected by electrically conductive plugs in required position, providing a predetermined function.
Recently, fabrication using copper has been introduced to solve problems such as RC delay caused by device feature size reduction responding to demands of increased device integrity. Moreover, copper also shows better heat conductivity, thus providing better electromigration resistance than conventional aluminum. Copper fabrication compatible with low dielectric constant (low-k) dielectric material has become a leading interconnect process in IC industry.
Nevertherless, one disadvantage of the copper fabrication is copper diffusing to the adjacent dielectric material, thus affecting reliability of the IC device, such that a metal barrier layer comprising material such as Ta or TaN is needed for diffusion suppression.
Moreover, another disadvantage of copper fabrication is the difficulty of copper etching, such that the copper fabrication is normally performed by damascene process, wherein a dielectric layer with a patterned opening for formation of a conductive layer therein is first formed by photolithography and subsequent etching. Next, a metal barrier and the copper metal sequentially fill the opening and unnecessary portions thereof beyond the opening are removed by planarization such as chemical mechanical polishing (CMP).
A conventional damascene process for forming interconnects is illustrated in cross section in FIGS. 1A–1C for better understanding.
In FIG. 1A, a semiconductor substrate 10 such as a silicon wafer with semiconductor devices or other existing conductive lines thereon is first provided, illustrated as a flat substrate 10 here for simplicity. Next, a first dielectric layer 12 is formed over the substrate 10 by a method such as chemical vapor deposition (CVD). A plurality of openings OP are then formed in the first dielectric layer 12 as metal layer patterns using known photolithography and etching. After formation of the openings OP, a first barrier layer 14 is conformably formed in each opening OP, covering the bottom surface and sidewalls thereof. Next, copper is formed over the first barrier layer 14, filling the openings OP, using electroplating. A planarization step such as chemical mechanical polishing (CMP) is then performed to remove unnecessary copper from the first dielectric layer 12, thus leaving first metal layer 16 in the openings, serving as conductive lines.
In FIG. 1B, an etching stop layer 18 and a second dielectric layer 20 are then deposited by, for example, chemical vapor deposition. Second openings OP′, each exposing a portion of the first metal layer 16 thereunder, are then formed in the second dielectric layer 20 and the etching stop layer 18 by known photolithography and etching, providing spaces for forming conductive plugs.
In FIG. 1C, a second barrier layer 22 is then conformably formed on the bottom surface and the sidewalls of each second opening OP′. Next, copper is formed over the second dielectric layer 20, filling the second openings OP′ by, for example, electroplating. Another planarization step such as chemical mechanical polishing (CMP) is performed to remove unnecessary copper from the second dielectric layer 20, thus leaving a second metal layer 24 in the second openings, serving as a conductive plug.
As shown in FIG. 1C, the barrier layers (referring to the first barrier 14 and the second barrier 22) typically comprise Ta or TaN (PVD) at a thickness of about 100–500 Å, formed by physical vapor deposition. These barrier layers are formed by physical vapor deposition and serve as diffusion barriers, suppressing diffusion of ions of the metal material, such as copper, from the conductive lines or conductive plugs (referring to the first metal layer 16 and the second metal layer 24) into the adjacent dielectric layers. In addition, the barrier layers also enhance adhesion of metal material of the metal layers to the dielectric layers.
Reliability problems, however, still may occur during damascene process using porous low-K material and the described metal barrier. The existing etching stop layer 18 also provides a possible leakage pathway, thus damaging testing results such as line-to-line leakage, time dependant dielectric breakdown (TDDB), RC delay or electromigration (EM) of an IC device.